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FT800Q-R 数据表(PDF) 26 Page - Bridgetek Pte Ltd. |
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FT800Q-R 数据表(HTML) 26 Page - Bridgetek Pte Ltd. |
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26 / 46 page ![]() Copyright © Bridgetek Pte Ltd 26 FT800 Embedded Video Engine Datasheet Version 1.4 Document No.: BRT_000039 Clearance No.: BRT#001 4.8 Power Management 4.8.1 Power supply The FT800 may be operated with a single supply of 3.3V apply to VCC and VCCIO pins. For operation with host MPU/MCU at lower supply, connect the VCCIO to MPU power to match the interface power. Symbol Typical Description VCCIO 1.8V, or 2.5V, or 3.3V Supply for Host interface digital I/O pad only, LCD RGB interface supply from VCC. VCC 3.3V Supply for chip Table 4-15 Power supply 4.8.2 Internal Regulator and POR The 1.2V internal regulator provides power to the core circuit. The regulator is disabled when device is in POWERDOWN state. Power down is activated either by the SCU command write or by holding down the PD_N pin for at least 5mS to allow the 1.2V decoupling capacitor to discharge fully. The regulator is enabled only by releasing the PD_N pin. A 47kΩ resistor is recommended to pull the PD_N pin up to VCCIO, together with a 100nF capacitor to ground in order to delay the 1.2V regulator powering up after the VCC and VCCIO are stable. The 1.2V internal regulator requires a compensation capacitor to be stable. A typical design puts a 4.7uF capacitor with ESR >0.5Ω is required between VCC1V2 to GND pins. Do not connect any load to this pin. The 1.2V regulator will generate Power-On-Reset (POR) pulse when the output voltage rises above the POR threshold. The POR will reset all the core digital circuits. It is possible to use PD_N pin as an asynchronous hardware reset input. Drive PD_N low for at least 5ms and then drive it high will reset the FT800 chip. Figure 4-8 1.2V regulator VCC PD_N VCC1V2 VCC GND GND GND VCCIO C R Cin 10uF 100nF 1.2V GND Ccomp 4.7uF 47k FT800 |
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