FT800Q-R datasheet(30/46 Pages) BRIDGETEK

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FT800 Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000039 Clearance No.: BRT#001

5 FT800 Memory Map

All memory and registers in the FT800 core are memory mapped in 22-bits address space with 2-bits

SPI/I2C command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 reserved

for Host Commands and 0'b11 undefined. The following are the memory space defined.

Start

Address

End

Address

Size

NAME

Description

00 0000h

03 FFFFh

256 kB

RAM_G

Main graphics RAM

0C 0000h

0C 0003h

4 B

ROM_CHIPID

FT800 chip identification and revision

information:

Byte [0:1] Chip ID: “0800”

Byte [2:3] Version ID: “0100”

0B B23Ch

0F FFFBh

275 kB

ROM_FONT

Font table and bitmap

0F FFFCh

0F FFFFh

4 B

ROM_FONT_ADDR

Font table pointer address

10 0000h

10 1FFFh

8 kB

RAM_DL

Display List RAM

10 2000h

10 23FFh

1 kB

RAM_PAL

Palette RAM

10 2400h

10 257Fh

380 B

REG_*

Registers

10 8000 h

10 8FFFh

4 kB

RAM_CMD

Command buffer

1C 2000 h

1C 27FFh

2 kB

RAM_SCREENSHOT

Screenshot readout buffer

Table 5-1 FT800 Memory Map

Note 1: The addresses beyond this table are reserved and shall not be read or written unless otherwise

specified.

Note 2: The ROM_CHIPID utilizes a part of shadow address from ROM_FONT address space.

5.1 FT800 Registers

Table 5.1 shows the complete list of the FT800 registers. Refer to FT800 Series Programmers Guide ,

Chapter 2 for details of the register function.

Address

Bits

Access

Reset

value

Description

102400h REG_ID

8 r/o

7Ch

Identification register, always reads as

7Ch

102404h

REG_FRAMES

32 r/o

000000

00h

Frame counter, since reset

102408h

REG_CLOCK

32 r/o

000000

00h

Clock cycles, since reset

10240Ch

REG_FREQUENCY

27 r/w

02DC6C

00h

Main clock frequency

102410h

REG_RENDERMODE

1 r/w

00h Rendering mode:

0 = normal, 1 = single-line

102414h

REG_SNAPY

9 r/w

00h Scan line select for RENDERMODE 1

102418h

REG_SNAPSHOT

1 r/o

- trigger for RENDERMODE 1

10241Ch

REG_CPURESET

1 r/w

00h Graphics, audio and touch engines

reset control

102420h

REG_TAP_CRC

32 r/o

- Live video tape crc. Frame CRC is

computed every DL SWAP.

102424h

REG_TAP_MASK

32 r/w

FFFFFFF

Live video tape mask

102428h

REG_HCYCLE

10 r/w

224h Horizontal total cycle count

10242Ch

REG_HOFFSET

10 r/w

02Bh Horizontal display start offset

102430h

REG_HSIZE

10 r/w

1E0h Horizontal display pixel count

102434h

REG_HSYNC0

10 r/w

000h Horizontal sync fall offset

102438h

REG_HSYNC1

10 r/w

029h Horizontal sync rise offset

10243Ch

REG_VCYCLE

10 r/w

124h Vertical total cycle count

102440h

REG_VOFFSET

10 r/w

00Ch Vertical display start offset

102444h

REG_VSIZE

10 r/w

110h Vertical display line count

102448h

REG_VSYNC0

10 r/w

000h Vertical sync fall offset

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