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FT800 Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000039 Clearance No.: BRT#001

4.2.2

Phase Locked Loop

The internal PLL takes input from the crystal oscillator. The PLL outputs clock to all internal circuits,

including graphics engine, audio engine and touch engine.

4.2.3

Clock Enable

Upon power on the FT800 enters standby mode, the system clock will be enabled when following steps

are executed:

Host sends an “ACTIVE” command (dummy read at address 0)

If the application choose to use the external clock source (12MHz crystal or clock), the following steps

shall be executed:

Host sends an “ACTIVE” command (dummy read at address 0)

Host sends an “CLKEXT” command

Host writes to REG_PCLK with non-zero value (i.e. 5)

If SPI is used as host interface, the SPI clock shall not exceed 11MHz before system clock is enabled.

After system clock is properly enabled, the SPI clock is allowed to go up to 30MHz.

4.2.4

Clock Frequency

Upon power-on the internal relaxation oscillator is untrimmed. The frequency range could be quite wide

from chip to chip (refer to table x-y for internal relaxation oscillator specifications). If the application

utilises the internal clock without external clock source, it is recommended to perform clock trimming by

software for better performance. For the details of clock trimming mechanism please refer to application

note AN_299_FT800_FT801_Internal_Clock_Trimming.

By default the system clock is 48MHz when the input clock is 12MHz. Host is allowed to switch the system

clock between 48MHz and 36MHz by the host command “CLK48MHz” and “CLK36MHz” respectively. The

clock switching is synchronised to VSYNC edge on the fly. This is to avoid possible graphics glitch during

clock switching. As a result, the clock switch will only take effect if the REG_PCLK is a non-zero value.

4.3 Graphics Engine

4.3.1

Introduction

The graphics engine executes the display list once for every horizontal line. It executes the primitive

objects in the display list and constructs the display line buffer. The horizontal pixel content in the line

buffer is updated if the object is visible at the horizontal line.

Main features of the graphics engine are:



The primitive objects supported by the graphics processor are: lines, points, rectangles, bitmaps

(comprehensive set of formats), text display, plotting bar graph, edge strips, and line strips, etc.



Operations such as stencil test, alpha blending and masking are useful for creating a rich set of

effects such as shadows, transitions, reveals, fades and wipes.



Anti-aliasing of the primitive objects (except bitmaps) gives a smoothing effect to the viewer.



Bitmap transformations enable operations such as translate, scale and rotate.



Display pixels are plotted with 1/16th pixel precision.



Four levels of graphics states



Tag buffer detection

The graphics engine also supports customized build-in widgets and functionalities such as jpeg decode,

screen saver, calibration etc. The graphics engine interprets commands from the MPU host via a 4 Kbyte

FIFO in FT800 memory at RAM_CMD. The MPU/MCU writes commands into the FIFO, and the graphics

engine reads and executes the commands. The MPU/MCU updates register REG_CMD_WRITE to indicate

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