TDA4VL...ALZQ1 datasheet(227/251 Pages) TI

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bit 1

bit 0

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

OLDI_CLK

OLDI_DATA[3:0]

TPP1

TPP2

TPP3

TPP4

TPP5

TPP6

TPP7

1UI

2UI

3UI

4UI

5UI

6UI

7UI

Δt

TPP

Figure 7-106. OLDI Transmitter Pulse Positions

DATA_TOL

0 V

Ideal Data

Bit End

DATA_TOL

Ideal Data

Bit Beginning

Sampling

Window

Ideal Center Position (t /2)

BIT

t (1UI)

BIT

OLDI_DATA[3:0]

Left

Right

Figure 7-107. OLDI Data Output Jitter

0 V

+VOD

-VOD

VSS=2 VOD

80%

20%

LLHT

OLDI_CLK

Figure 7-108. LVDS Output Transition Times

For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device

TRM.

7.10.5.21 PCIE

The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the

specification for timing details.

For more details about features and additional description information on the device Peripheral Component

Interconnect Express, see the corresponding sections within Signal Descriptions and Detailed Description.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter in the device TRM.

7.10.5.22 Timers

For more details about features and additional description information on the device Timers, see the

corresponding sections within Signal Descriptions and Detailed Description.

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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

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