TDA4VL...ALZQ1 datasheet(225/251 Pages) TI

部件名	TDA4VL...ALZQ1

功能描述	TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

PDF	251 Pages

Scroll/Zoom	100%

制造商	TI [Texas Instruments]

网页	http://www.ti.com

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7.10.5.19.2.2 OSPI0 Tap DDR Timing

Table 7-88, Figure 7-104, Table 7-89, and Figure 7-105 present timing requirements and switching

characteristics for OSPI0 Tap DDR Mode.

Table 7-88. OSPI0/1 Timing Requirements – Tap DDR Mode

see Figure 7-104

NO.

MODE

MIN

MAX

UNIT

O13

tsu(D-CLK)

Setup time, OSPI0/1_D[7:0] valid before

active OSPI0/1_CLK edge

No Loopback

(12.04 -

(0.975T(1)R(2)))

O14

th(CLK-D)

Hold time, OSPI0/1_D[7:0] valid after

active OSPI0/1_CLK edge

No Loopback

(1.84 +

(0.975T(1)R(2)))

(1)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2)

R = refclk cycle time in ns

OSPI_CLK

O14

O13

OSPI_TIMING_03

OSPI_D[i:0]

O14

O13

Figure 7-104. OSPI0/1 Timing Requirements – Tap DDR, No Loopback

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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

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