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TDA4VL...ALZQ1 数据表(PDF) 221 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 221 Page - Texas Instruments |
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221 / 251 page  Table 7-84. OSPI DLL Delay Mapping - DDR Timing Modes (continued) MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD OSPI0 OSPI1 DELAY VALUE 1.8V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x23 0x29 3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x47 0x42 All other modes PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 0x0 Table 7-85. OSPI Timing Requirements – DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK (DQS) edge(1) 1.8V, External Board Loopback 0.52 ns 3.3V, External Board Loopback 1.97 ns O16 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK (DQS) edge(1) 1.8V, External Board Loopback 1.24 (2) ns 3.3V, External Board Loopback 1.44 (2) ns O17 tsu(D-DQS) Setup time, DQS edge to D[i:0] transition(1) 1.8V, DQS –0.46 ns 3.3V, DQS –0.66 ns O18 th(DQS-D) Hold time, DQS edge to D[i:0] transition(1) 1.8V, DQS 3.59 ns 3.3V, DQS 8.89 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to OSPI and QSPI Board Design and Layout Guidelines for more details. OSPI_DQS O16 O15 OSPI_TIMING_04 OSPI_D[i:0] Figure 7-100. OSPI Timing Requirements – DDR, External Loopback Clock and DQS 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, CLK 1.8V 19 ns 3.3V 19 ns O2 tw(CLKL) Pulse duration, CLK low 0.475*P - 0.3 (2) ns O3 tw(CLKH) Pulse duration, CLK high 0.475*P - 0.3 (2) ns O4 td(CLK-CSn) Delay time, CSn active edge to CLK rising edge 1.8V 0.475 * P + 0.975 * M * R - 7 (2) (3) (5) 0.525 * P + 1.025 * M * R + 1(2) (3) (5) ns 3.3V 0.475 * P + 0.975 * M * R - 7(2) (3) (5) 0.525 * P + 1.025 * M * R + 1(2) (3) (5) ns O5 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V 0.475 * P + 0.975 * N * R - 7(2) (4) (5) 0.525 * P + 1.025 * N * R + 1 (2) (4) (5) ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX 0.475 * P + 0.975 * N * R - 7(2) (4) (5) 0.525 * P + 1.025 * N * R + 1 (2) (4) (5) ns www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 221 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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