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TDA4VL...ALZQ1 数据表(PDF) 220 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 220 Page - Texas Instruments |
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220 / 251 page  7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O7 tc(CLK) Cycle time, CLK 1.8V 7 ns 3.3V 7.5 ns O8 tw(CLKL) Pulse duration, CLK low –0.3+0.475*P (2) ns O9 Pulse duration, CLK high –0.3+0.475*P (2) ns O10 ttd(CSn-CLK) Delay time, CSn[3:0] active edge to CLK rising edge 1.8V 0.475 * P + 0.975 * M * R - 7 (2) (3) (5) 0.525 * P + 1.025 * M * R + 1 (2) (3) (5) ns 3.3V 0.475 * P + 0.975 * M * R - 7(2) (3) (5) 0.525 * P + 1.025 * M * R + 1 (2) (3) (5) ns O11 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V 0.475 * P + 0.975 * N * R - 1 (2) (4) (5) 0.525 * P + 1.025 * N * R + 1 (2) (4) (5) ns 3.3V 0.475 * P + 0.975 * N * R - 1 (2) (4) (5) 0.525 * P + 1.025 * N * R + 1(2) (4) (5) ns O12 td(CLK-D) Delay time, CLK active edge to D[i:0] transition(1) 1.8V –1.16 1.25 ns 3.3V –1.33 1.51 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time = SCLK period (3) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (5) R = refclk OSPI_CLK OSPI_TIMING_02 OSPI_CSn O10 O11 O9 O8 O12 O7 OSPI_D[i:0] Figure 7-99. OSPI Switching Characteristics – SDR Section 7.10.5.19.1.2.3, Section 7.10.5.19.1.2.1, Section 7.10.5.19.1.2.2, Section 7.10.5.19.1.2.2, and Figure 7-98 presents timing requirements for OSPI DDR and SDR Mode. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode Table 7-84. OSPI DLL Delay Mapping - DDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD OSPI0 OSPI1 DELAY VALUE TRANSMIT 1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x54 0x54 3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x55 0x5C RECEIVE TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 220 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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