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TDA4VL...ALZQ1 数据表(PDF) 216 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 216 Page - Texas Instruments |
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216 / 251 page  7.10.5.17.2.7 UHS–I SDR104 Mode Table 7-79, and Figure 7-95 present switching characteristics for MMC1/2 – UHS-I SDR104 Mode. Table 7-79. MMC1/2 Switching Characteristics – UHS-I SDR104 Mode see Figure 7-95 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 200 MHz SDR1045 tc(clk) Cycle time, MMC[x]_CLK 5 ns SDR1046 tw(clkH) Pulse duration, MMC[x]_CLK high 2.12 ns SDR1047 tw(clkL) Pulse duration, MMC[x]_CLK low 2.12 ns SDR1048 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 1.07 3.21 ns SDR1049 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 1.07 3.21 ns A. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR1045 SDR1047 SDR1046 SDR1048 SDR1049 SDR1048 SDR1049 Figure 7-95. MMC1/2 – UHS-I SDR104 – Transmit Mode 7.10.5.18 CPTS Table 7-80 represents CPTS timing conditions. Table 7-80. CPTS Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 10 pF Section 7.10.5.18.1, Section 7.10.5.18.2, Figure 7-96, and Figure 7-97 present timing requirements and switching characteristics of the CPTS interface. 7.10.5.18.1 CPTS Timing Requirements see Figure 7-96 NO. MIN MAX UNIT T1 tw(HWnTSPUSHH) Pulse duration, HWnTSPUSH(2) high 12P + 2(1) ns T2 tw(HWnTSPUSHL) Pulse duration, HWnTSPUSH(2) low 12P + 2(1) ns T3 tc(RFT_CLK) Cycle time, RFT_CLK 5 8 ns T4 tw(RFT_CLKH) Pulse duration, RFT_CLK high 0.45 * T(3) ns T5 tw(RFT_CLKL) Pulse duration, RFT_CLK low 0.45 * T(3) ns (1) P = functional clock period in ns. (2) In HWnTSPUSH, n = 1 to 2. (3) T = RFT_CLK period in ns. TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 216 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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