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TDA4VL...ALZQ1 数据表(PDF) 212 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 212 Page - Texas Instruments |
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212 / 251 page  7.10.5.17.2.3 UHS–I SDR12 Mode Table 7-73, Figure 7-89, Table 7-74, and Figure 7-90 present timing requirements and switching characteristics for MMC1/2 – UHS-I SDR12 Mode. Table 7-73. MMC1/2 Timing Requirements – UHS-I SDR12 Mode see Figure 7-89 NO. MIN MAX UNIT SDR121 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 5.46 ns SDR122 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 1.67 ns SDR123 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 5.46 ns SDR124 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 1.67 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x SDR121 SDR122 SDR123 SDR124 MMC[ ]_CLK x Figure 7-89. MMC1/2 – UHS-I SDR12 – Receive Mode Table 7-74. MMC1/2 Switching Characteristics – UHS-I SDR12 Mode see Figure 7-90 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 25 MHz SDR125 tc(clk) Cycle time, MMC[x]_CLK 40 ns SDR126 tw(clkH) Pulse duration, MMC[x]_CLK high 18.7 ns SDR127 tw(clkL) Pulse duration, MMC[x]_CLK low 18.7 ns SDR128 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 1.2 13.55 ns SDR129 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 1.2 13.55 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR125 SDR127 SDR126 SDR128 SDR129 SDR128 SDR129 Figure 7-90. MMC1/2 – UHS-I SDR12 – Transmit Mode TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 212 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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