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TDA4VL...ALZQ1 数据表(PDF) 211 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 211 Page - Texas Instruments |
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211 / 251 page  7.10.5.17.2.2 High Speed Mode Table 7-71, Figure 7-87, Table 7-72, and Figure 7-88 present timing requirements and switching characteristics for MMC1/2 – High Speed Mode. Table 7-71. MMC1/2 Timing Requirements – High Speed Mode see Figure 7-87 NO. MIN MAX UNIT HS1 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.15 ns HS2 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 2.26 ns HS3 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.15 ns HS4 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 2.26 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLK x MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x H 1 S H 2 S H 3 S H 4 S Figure 7-87. MMC1 /2– High Speed – Receive Mode Table 7-72. MMC1/2 Switching Characteristics – High Speed Mode see Figure 7-88 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 50 MHz HS5 tc(clk) Cycle time. MMC[x]_CLK 20 ns HS6 tw(clkH) Pulse duration, MMC[x]_CLK high 9.2 ns HS7 tw(clkL) Pulse duration, MMC[x]_CLK low 9.2 ns HS8 td(clkL-cmdV) Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition –2.07 2.07 ns HS9 td(clkL-dV) Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition –2.07 2.07 ns MMC[x]_CLK MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x H 5 S H 7 S H 8 S H 9 S HS6 Figure 7-88. MMC1/2 – High Speed – Transmit Mode www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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