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TDA4VL...ALZQ1 数据表(PDF) 213 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 213 Page - Texas Instruments |
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213 / 251 page  7.10.5.17.2.4 UHS–I SDR25 Mode Table 7-75, Figure 7-91, Table 7-76, and Figure 7-92 present timing requirements and switching characteristics for MMC1/2 – UHS-I SDR25 Mode. Table 7-75. MMC1/2 Timing Requirements – UHS-I SDR25 Mode see Figure 7-91 NO. MIN MAX UNIT SDR251 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.1 ns SDR252 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 1.67 ns SDR253 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.1 ns SDR254 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 1.67 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLK x MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x SDR251 SDR252 SDR253 SDR254 Figure 7-91. MMC1/2 – UHS-I SDR25 – Receive Mode Table 7-76. MMC1/2 Switching Characteristics – UHS-I SDR25 Mode see Figure 7-92 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 50 MHz SDR255 tc(clk) Cycle time, MMC[x]_CLK 20 ns SDR256 tw(clkH) Pulse duration, MMC[x]_CLK high 9.2 ns SDR257 tw(clkL) Pulse duration, MMC[x]_CLK low 9.2 ns SDR258 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 2.4 9.37 ns SDR259 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 2.4 9.37 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ _ [3:0] x] SDR255 SDR257 SDR256 SDR258 SDR259 SDR258 SDR259 Figure 7-92. MMC1/2 – UHS-I SDR25 – Transmit Mode www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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