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TDA4VL...ALZQ1 数据表(PDF) 210 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 210 Page - Texas Instruments |
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210 / 251 page  7.10.5.17.2.1 Default Speed Mode Table 7-69, Figure 7-85, Table 7-70, and Figure 7-86 present timing requirements and switching characteristics for MMC1/2 – Default Speed Mode. Table 7-69. MMC1/2 Timing Requirements – Default Speed Mode see Figure 7-85 NO. MIN MAX UNIT DS1 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.15 ns DS2 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 4.56 ns DS3 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.15 ns DS4 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 4.56 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLK x M [ ]_ MC CMD x MMC DAT [ ]_ [3:0] x DS1 DS2 DS3 DS4 Figure 7-85. MMC1/2 – Default Speed – Receive Mode Table 7-70. MMC1/2 Switching Characteristics – Default Speed Mode see Figure 7-86 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 25 MHz DS5 tc(clk) Cycle time, MMC[x]_CLK 40 ns DS6 tw(clkH) Pulse duration, MMC[x]_CLK high 18.7 ns DS7 tw(clkL) Pulse duration, MMC[x]_CLK low 18.7 ns DS8 td(clkL-cmdV) Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition –3.53 3.53 ns DS9 td(clkL-dV) Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition –3.53 3.53 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ _ [3:0] x] D 5 S D 7 S D 8 S D 9 S DS6 Figure 7-86. MMC1/2 – Default Speed – Transmit Mode TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 210 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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