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TDA4VL...ALZQ1 数据表(PDF) 232 Page - Texas Instruments

部件名 TDA4VL...ALZQ1
功能描述  TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0
PDF  251 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4VL...ALZQ1 数据表(HTML) 232 Page - Texas Instruments

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1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in
this table only apply when the two IO power domains are operating at the same voltage. Values for these
timing parameters are not defined when operating the two IO power domains at different voltages since
propagation delay through the device IO buffers differ when some are operating at 1.8V while others are
operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG
interface is still expected to function when the two IO power domains are operated at different voltages,
assuming the system designer has implemented appropriate level shifters and the operating frequency is
reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different
voltages.
TDO
J2
J1
J4
TCK
J5
TDI / TMS
J3
J6
J7
J4
J5
Figure 7-112. JTAG Timing Requirements and Switching Characteristics
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1
SPRSP62 – DECEMBER 2022
www.ti.com
232
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1



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