KSZ9563R datasheet(210/226 Pages) MICROCHIP

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KSZ9563R

DS00002419D-page 210

 2017-2018 Microchip Technology Inc.

6.4.8

POWER-UP AND RESET TIMING

Figure 6-13 illustrates the power-up and reset timing requirements.

FIGURE 6-13:

POWER-UP AND RESET TIMING

TABLE 6-12:

POWER-UP AND RESET TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

tvr

Supply voltage rise time (must be monotonic)

200

s

tsr

Stable supply voltages to de-assertion of reset

tcs

Strap-in pin configuration setup time

tch

Strap-in pin configuration hold time

trc

De-assertion of reset to strap-in pin output

tpc

Supply voltages cycle off-to-on time

150

trw

Reset pulse width after power-up (warm reset)

s

Note 1: The recommended powering sequence is to bring up VDDIO first, then core (DVDDL, AVDDL), and fol-

lowed by AVDDH. However, if VDDIO and AVDDH share the same power supply, then the recommended

power-up sequence is to power-up core (DVDLL, AVDDL) first and then the shared power supply for

VDDIO and AVDDH. The power-up waveforms should be monotonic for all supply voltages.

Note 2: After the de-assertion of reset, it is recommended to wait a minimum of 100

s before starting to program

the device through any interface.

Note 3: The recommended power down sequence is to power down the low voltage core before powering down

the transceiver and digital I/O voltages, or to have all supplies power down in unison.

Before the next power-up cycle, all supply voltages to the device should reach less than 0.4V and there

should be a minimum wait time of 150ms from power-off to power-on.

tsr

tcs

tch

trc

SUPPLY

VOLTAGES

RESET_N

STRAP-IN

VALUE

STRAP-IN /

OUTPUT PIN

CORE (AVDDL, DVDDL)

TRANSCEIVER (AVDDH), DIGITAL I/Os (VDDIO)

tvr

tpc

NOTE

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