KSZ9563RNXI-TR datasheet(189/226 Pages) MICROCHIP

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DS00002419D-page 189

KSZ9563R

TABLE 5-4:

VLAN TABLE DATA FIELDS

5.3.4.1

VLAN Table Write Operation

Write to the VLAN Table Entry 0 Register, VLAN Table Entry 1 Register, and VLAN Table Entry 2 Register to set

up the data fields as described in Figure 5-4 and Table 5-4.

Write the VLAN Index value in the VLAN Table Index Register. This is the 12-bit index (address) to select the

table entry. It is equivalent to the VID which indexes the table during lookup.

Write the VLAN Table Access Control Register to specify a write operation, and set START (bit 7). When the oper-

ation is complete, bit 7 will be cleared automatically.

5.3.4.2

VLAN Table Read Operation

Write the VLAN Index value in the VLAN Table Index Register to select one of the 4k table entries.

Write the VLAN Table Access Control Register to specify a read operation and set START (bit 7). When the oper-

ation is complete, bit 7 will be cleared automatically.

Read the VLAN Table Entry 0 Register, VLAN Table Entry 1 Register, and VLAN Table Entry 2 Register to retrieve

the read results from the VLAN table.

5.3.5

ACCESS CONTROL LIST (ACL) TABLE

ACL filtering is implemented individually per-port. The ACL tables are accessed using the Port N: Port Switch ACL Con-

trol Registers (0xN600 - 0xN6FF). The 16 entries in each ACL table are addressed indirectly by an index register.

Table 5-5 shows how the various fields of the ACL Table entries are mapped to data registers. The Port ACL Byte Enable

MSB Register and Port ACL Byte Enable LSB Register make it possible to write or read any combination of bytes. This

is useful for writing the Matching rule, Action rule and Process field separately. There are 16 bits in these byte enable

registers, corresponding to the 16 data registers Port ACL Access 0 Register through Port ACL Access F Register. Note

that the enable bits are applied in reverse order:

Bit 0 for the Port ACL Access F Register

Bit 1 for the Port ACL Access E Register

…

Bit 14 for the Port ACL Access 1 Register

Bit 15 for the Port ACL Access 0 Register

Also note that the Port ACL Access C Register is not used, so byte enable bit 3 is a don't care.

Field

Size (bits)

Description

VALID

When 1, indicates that the table entry is valid.

FORWARD OPTION

When 1, forward to VLAN port table (PORT FORWARD field).

When 0, see Table 4-8, "VLAN Forwarding" for details.

PRIORITY

Priority value for this VID.

MSTP INDEX

Multiple Spanning Tree Protocol index.

FID

Filter ID value. It is combined with destination address and hashed to index

the Address Lookup Table.

PORT UNTAG

(1 per port)

When 1, untag at that egress port.

When 0, don’t untag.

Note: Port 1 is the LSB, followed by Port 2, and so on. Bits 4-7 are reserved.

PORT FORWARD

(1 per port)

VLAN port membership list. There is one bit per port, starting with the LSB

which corresponds to port 1.

A bit value of 1 indicates the associated port is included in the port

membership list for that VID.

When 0, that port is excluded.

Note: Port 1 is the LSB, followed by Port 2, and so on. Bits 4-7 are reserved.

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