KSZ9563RNXI-TR datasheet(47/226 Pages) MICROCHIP

47 / 226 page

 2017-2018 Microchip Technology Inc.

DS00002419D-page 47

KSZ9563R

4.4.17.5

ACL Registers

Table 4-22 provides a list of ACL related registers.

4.5

IEEE 1588 Precision Time Protocol

The IEEE 1588 precision time protocol (PTP) provides a method for establishing time synchronization across nodes in

a network. The device supports V2 (2008) of the IEEE 1588 PTP specification and can be programmed as either an

end-to-end (E2E) or peer-to-peer (P2P) transparent clock (TC) between ports. In addition, the host port can be pro-

grammed as either a slave or master ordinary clock (OC) port. Ingress timestamp capture, egress timestamp recording,

correction field update with residence time and link delay, delay turn-around time insertion, egress timestamp insertion,

and checksum update are supported. PTP frame filtering is implemented to enhance overall system performance. Delay

adjustments are implemented to fine tune the synchronization. Versatile event trigger outputs and timestamp capture

inputs are implemented to meet various real time application requirements through the GPIO_1 and GPIO_2 pins.

The key features of the IEEE 1588 implementation are:

• One-step event message format

• Implementation of precision time clock per specification

- Upper 16 bits of the second clock not implemented

• Both E2E and P2P TC

• Both slave and master OC

• PTP multicast and unicast addressing

• Transport of PTP over IPv4/IPv6 UDP and IEEE 802.3/Ethernet

• Precision time stamping of input signal on the GPIO_1 and GPIO_2 pins

• Creation and delivery of clock, pulses, or other unique serial bit stream on the GPIO_1 and GPIO_2 pins with

respect to the precision time clock time.

IEEE 1588 defines two essential functions: The measurement of link and residence (switching) delays by using the

Delay_Req/Resp or Pdelay_Req/Resp messages, and the distribution of time information by using the Sync/Follow_Up

messages. The 1588 PTP event messages are periodically sent from the grandmaster in the network to all slave clock

devices. Link delays are measured by each slave node to all its link partners to compensate for the delay of PTP mes-

sages sent through the network.

All PHY ports must be operating at 100Mbps or 1Gbps when implementing IEEE 1588. It is not compatible with 10Mbps.

4.5.1

IEEE 1588 PTP SYSTEM TIME CLOCK

The device’s system time clock (STC) is a readable and writable high-precision counter that is used to keep the PTP

time. The counter resolution is 2-32ns. Figure 4-9 details the PTP Clock.

TABLE 4-22:

ACL REGISTERS

Registers

Description

Port Interrupt Status Register,

Port Interrupt Mask Register

ACL interrupt

Port ACL Access 0 Register through

Port ACL Access F Register,

Port ACL Byte Enable MSB Register,

Port ACL Byte Enable LSB Register,

Port ACL Access Control 0 Register

ACL Table access

Port Priority Control Register

Priority classification

Port Authentication Control Register

ACL enable

KSZ9563RNXI-TR 数据表(PDF) 47 Page - Microchip Technology

KSZ9563RNXI-TR 数据表(HTML) 47 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载