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KSZ9563RNXI-TR 数据表(PDF) 15 Page - Microchip Technology |
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KSZ9563RNXI-TR 数据表(HTML) 15 Page - Microchip Technology |
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15 / 226 page ![]() 2017-2018 Microchip Technology Inc. DS00002419D-page 15 KSZ9563R Miscellaneous Pins Interrupt INTRP_N OPU Active low, open-drain interrupt. Note: This pin requires an external pull-up resistor. Power Management Event PME_N IPU/O8 Power Management Event. This output signal indicates that an energy detect event has occurred. It is intended to be used as a system request to wake up from a low power mode. Note: The assertion polarity is programmable (default active low). An external pull-up resistor is required for active-low operation; an external pull-down resistor is required for active-high operation. Note: This pin also provides configuration strap func- tions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for addi- tional information. System Reset RESET_N IPU Active low system reset. The device must be reset either during or after power-on. An RC circuit is suggested for power-on reset. Crystal Clock / Oscillator Input XI ICLK Crystal clock / oscillator input. When using a 25MHz crystal, this input is connected to one lead of the crystal. When using a 2.5V oscillator, this pin is the input from the oscillator. The crystal oscillator should have a tolerance of ±50ppm. Crystal Clock Output XO OCLK Crystal clock / oscillator output. When using a 25MHz crystal, this output is connected to one lead of the crystal. When using a 2.5V oscillator, this pin is left unconnected. General Purpose Input/Output 1 GPIO_1 IPU/O8 This signal can be used for IEEE 1588 applications and is synchronized to the IEEE 1588 clock. It can be pro- grammed as an input for timestamp capture, or an output for even trigger. A host processor can be used to control (as an output) or sample (as an input) this signal via device reg- isters. General Purpose Input/Output 2 GPIO_2 IPU/O8 This signal can be used for IEEE 1588 applications and is synchronized to the IEEE 1588 clock. It can be pro- grammed as an input for timestamp capture, or an output for even trigger. A host processor can be used to control (as an output) or sample (as an input) this signal via device reg- isters. Transmit Output Current Set Resistor ISET A Transmit output current set resistor. This pin configures the physical transmit output current. It must be connected to GND through a 6.04kΩ 1% resistor. Power/Ground Pins +3.3/2.5/1.8V I/O Power VDDIO P +3.3V / +2.5V / +1.8V I/O Power +3.3/2.5V Analog Power AVDDH P +3.3V / +2.5V Analog Power +1.2V Analog Power AVDDL P +1.2V Analog Power TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description |
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