KSZ9563RNXI-TR datasheet(52/226 Pages) MICROCHIP

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KSZ9563R

DS00002419D-page 52

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or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization

stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, as

long as the 16 duplications of the IEEE address match the address of the machine to be awakened.

4.8.6.4

Interrupt Generation on Power Management Related Events

There are two ways an interrupt can be generated to the host whenever a power management related event takes place.

The resulting interrupts are via the PME_N signal pin or via the INTRP_N signal pin.

4.9

Management Interface

The management interface may be used by an external host processor to read and write the device’s registers. This

interface has three available modes of operation: SPI, I2C or MIIM. The interface mode is selected at the deassertion

of reset by a strapping option (refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information).

Of the three interface options, SPI provides the highest performance, while MIIM performance is the lowest. Most impor-

tantly, MIIM provides access to the PHY control and status registers, but not to any of the switch registers. The vast

majority of applications therefore can use SPI or I2C, but not MIIM.

4.10, "In-Band Management," on page 56. Because the in-band management interface must be set up via the SPI or

I2C interface before it can be used, it can complement but not completely replace the serial management interface.

4.9.1

SPI SLAVE SERIAL BUS

The KSZ9563R supports a slave mode SPI interface that provides complete access to all device registers via an SPI

master device. The SPI master device supplies the serial clock (SCL), select (SCS_N), and serial input data (SDI). Serial

output data (SDO) is driven by the KSZ9563R.

SCL is expected to stay low when SPI operation is idle. SPI operations start with the falling edge of SCS_N and end with

the rising edge of SCS_N. A single read or write access consists of a 27-bit command/address phase, then a 5-bit turn-

around (TA) phase, then an 8-bit data phase. For burst read or write access, SCS_N is held low while SCL continues to

toggle. For every 8 cycles of SCL, the device will increment the address counter, and the corresponding data byte will

be transferred on SDI or SDO in succession.

All commands, addresses and data are transferred most significant bit first. Input data on SDI is latched on the rising

edge of serial clock SCL. Output data on SDO is clocked on the falling edge of SCL.

As shown in Figure 4-24, there are two commands: register read and register write. Figure 4-11 and Figure 4-12 show

the timing for these two operations.

Note 4-8

TA bits are turn-around bits. They are “don't care” bits.

TABLE 4-24:

SPI Operation

Command/Address Phase (SDI pin)

TA bits

(Note 4-8)

Data Phase

(SDO or SDI pins)

Command

011

A23 A22 A21 A20 … A7 A6 A5 A4 A3 A2 A1 A0 XXXXX D7 D6 D5 D4 D3 D2 D1 D0

010

A23 A22 A21 A20 … A7 A6 A5 A4 A3 A2 A1 A0 XXXXX D7 D6 D5 D4 D3 D2 D1 D0

Note:

The actual device address space is 16 bits (A15 - A0), so the values of address bits A23 - A16 in the SPI

command/address phase are “don't care”.

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