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KSZ9563RNXI-TR 数据表(PDF) 200 Page - Microchip Technology |
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KSZ9563RNXI-TR 数据表(HTML) 200 Page - Microchip Technology |
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200 / 226 page  KSZ9563R DS00002419D-page 200 2017-2018 Microchip Technology Inc. be disabled by clearing the RGMII Egress Internal Delay bit in the XMII Port Control 1 Register register. Generally this is not recommended. Note 6-5 For 10Mbps and 100Mbps, TCYC will scale to 400ns +/- 40ns and 40ns +/- 4 ns, respectively. Note 6-6 0.75ns for VDDIO = 3.3V/2.5V, 1.5ns for VDDIO = 1.8V 6.4.2 MII TIMING 6.4.2.1 MII Output Timing in MAC Mode Figure 6-2 illustrates a write operation from the KSZ9563R to a PHY or other device while operating the KSZ9563R in MAC Mode. FIGURE 6-2: MII OUTPUT TIMING IN MAC MODE TABLE 6-3: MII OUTPUT TIMING IN MAC MODE VALUES Symbol Description Min Typ Max Units tP (100BASE-TX / 10BASE-T) RX_CLK period 40/400 ns tWL (100BASE-TX / 10BASE-T) RX_CLK pulse width low 20/200 ns tWH (100BASE-TX / 10BASE-T) RX_CLK pulse width high 20/200 ns tOD RX_DV, RXD[3:0] output delay from rising edge of RX_CLK 16 ns |
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