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KSZ9563RNXI-TR 数据表(PDF) 153 Page - Microchip Technology |
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KSZ9563RNXI-TR 数据表(HTML) 153 Page - Microchip Technology |
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153 / 226 page  2017-2018 Microchip Technology Inc. DS00002419D-page 153 KSZ9563R 5.2.4.2 Port MAC Control 1 Register 5.2.4.3 Port Ingress Rate Limit Control Register Address: 0xN401 Port N: 1-3 Size: 8 bits Bits Description Type Default 7 RESERVED R/W 0b 6 RESERVED RO 0b 5:4 RESERVED R/W 00b 3 Back pressure Enable Back pressure is used only for half duplex. Full duplex uses PAUSE frame flow control which is enabled separately. 1 = Enable port back pressure 0 = Disable port back pressure R/W 0b 2:1 Reserved R/W 00b 0 Pass All Frames Bad frames (CRC error, too large, too small) are normally dropped. This feature allows them to be forwarded for mirroring purposes only. This bit does not affect filtering of flow control frames. To disable filtering of flow control frames, refer to the Switch MAC Control 4 Register. 1 = Enable 0 = Disable R/W 0b Address: 0xN403 Port N: 1-3 Size: 8 bits Bits Description Type Default 7 RESERVED RO 0b 6 Port or Priority Based Ingress Rate Limiting 1 = Ingress rate limiting is port based 0 = Ingress rate limiting is priority based R/W 0b 5 Ingress PPS Mode 1 = Ingress rate limiting is based on number of packets (PPS mode enabled) 0 = Ingress rate limiting is based on number of bits (PPS mode disabled) R/W 0b 4 Ingress Rate Limit Flow Control Enable To use this feature, flow control must also be enabled for this port. Refer to the XMII Port Control 0 Register for non-PHY ports, and the PHY Auto- Negotiation Advertisement Register for PHY ports. 1 = Flow control is asserted if the port’s receive rate is exceeded 0 = Flow control is not asserted based on ingress rate limits R/W 0b |
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