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数据搜索系统，热门电子元器件搜索 |
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UPSD325X 数据表(PDF) 52 Page - STMicroelectronics |
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UPSD325X 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 176 page  µPSD325X DEVICES 52/176 Watchdog reset pulse width depends on the clock frequency. The reset period is Tfosc x 12 x 222 The RESET pulse width is Tfosc x 12 x 215. Figure 21. RESET Pulse Width Table 34. Watchdog Timer Clear Register (WDRST: 0A6H) Table 35. Description of the WDRST Bits Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled. 76543210 Reserved WDRST6 WDRST5 WDRST4 WDRST3 WDRST2 WDRST1 WDRST0 Bit Symbol Function 7 — Reserved 6 to 0 WDRST6 to WDRST0 To reset watchdog timer, write any value beteen 00h and 7Eh to this register. This value is loaded to the 7 most significant bits of the 22-bit counter. For example: MOV WDRST,#1EH Reset period (1.258 second at 40Mhz) (about 6.291 seconds at 8Mhz) Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz) AI06823 |
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