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UPSD325X 数据表(PDF) 65 Page - STMicroelectronics |
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UPSD325X 数据表(HTML) 65 Page - STMicroelectronics |
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65 / 176 page  65/176 µPSD325X DEVICES 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. Figure 27. Serial Port Mode 0, Block Diagram AI06824 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Shift Clock Serial Port Interrupt S6 REN R1 Rx Clock Start Tx Clock Start Shift Shift Send Receive T R CL DS Q 7 6 5 4 3 2 1 0 RxD P3.0 Alt Input Function RxD P3.0 Alt Output Function TxD P3.1 Alt Output Function |
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