UPSD325X datasheet(88/176 Pages) STMICROELECTRONICS

88 / 176 page

µPSD325X DEVICES

88/176

DDC1 Protocol

DDC1 is primitive and a point to point interface.

The monitor is always put at “Transmit only” mode.

In the initialization phase, 9 clock cycles on VCLK

pin will be given for the internal synchronization.

During this period, the SDA pin will be kept at high

impedance state.

If DDC1 hardware mode is used, the following pro-

cedure is recommended to proceed DDC1 opera-

tion.

1. Reset DDC1 enable (by default, DDC1 enable is

cleared as LOW after Power-on Reset).

2. Set SWENB as high (the default value is zero.)

3. Depending on the data size of EDID data, set

EX_DAT as LOW (128 bytes) or HIGH (256

bytes).

4. By using bulky moving commands (DDCADR,

RAMBUF involved) to move the entire EDID

data to RAM buffer.

5. Reset SWENB to LOW.

6. Reset DDCADR to 00h.

7. Set DDC1 enable as HIGH.

In case SWENB is set as high, interrupt service

routine is finished within 133 machine cycle in

40MHz System clock.

The maximum VSYNC (VCLK) frequency is 25Khz

(40µs). And the 9th clock of VSYNC (VCLK) is inter-

rupt period.

So the machine cycle be needed is calculated as

below. For example,

When 40MHz system clock, 40µs = 133 x (25ns x

12); 133 machine cycle.

12MHz system clock, 40µs = 40 x (83.3ns x 12);

40 machine cycle.

8MHz system clock, 40µs = 26 x (125ns x 12); 26

machine cycle.

Note: If EX_DAT equals to LOW, it is meant the

lower part is occupied by DDC1 operation and the

upper part is still free to the system. Nevertheless,

the effect of the post increment just applies to the

part related to DDC1 operation. In other words, the

system program is still able to address the loca-

tions from 128 to 255 in the RAM buffer through

MOVX command but without the facility of the post

increment. For example, the case of accessing

200 of the RAM Buffer:

MOV R0, #200, and

MOVX A, @R0

Figure 42. Transmission Protocol in the DDC1 Interface

AI06652

123456789123456

7891

tSU(DDC1)

tDOV

Hi-Z

VCLK

DDC1INT

DDC1EN

tH(VCLK)

tL(VCLK)

Max=40us

BBBBB

HiZ

UPSD325X 数据表(PDF) 88 Page - STMicroelectronics

UPSD325X 数据表(HTML) 88 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载