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UPSD325X 数据表(PDF) 41 Page - STMicroelectronics |
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UPSD325X 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 176 page ![]() 41/176 µPSD325X DEVICES Table 18. SFR Register Interrupt Priority Structure Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority special function register IP and IPA. 0 = low priority 1 = high priority A low priority interrupt may be interrupted by a high priority interrupt level interrupt. A high priority interrupt routine cannot be interrupted by any oth- er interrupt source. If two interrupts of different pri- ority occur simultaneously, the high priority level request is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling se- quence. Interrupts Enable Structure Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the inter- rupt enable special function register IE and IEA. All interrupt source can also be globally disabled by clearing Bit EA in IE. Table 19. Priority Levels Table 20. Description of the IE Bits SFR Addr Reg Name Bit Register Name Reset Value Comments 76 5 4 3 2 1 0 A7 IEA EDDC —— ES2 — — EI2C EUSB 00 Interrupt Enable (2nd) A8 IE EA — ET2 ES ET1 EX1 ET0 EX0 00 Interrupt Enable B7 IPA PDDC — — PS2 — — PI2C PUSB 00 Interrupt Priority (2nd) B8 IP — — PT2 PS PT1 PX1 PT0 PX0 00 Interrupt Priority Source Priority with Level Int0 0 (highest) 2nd USART 1 Timer0 2 I²C 3 Int1 4 DDC 5 Timer1 6 USB 7 1st USART 8 Timer2+EXF2 9 (lowest) Bit Symbol Function 7EA Disable all interrupts: 0: no interrupt with be acknowledged 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit 6 — Reserved 5 ET2 Enable Timer2 interrupt 4 ES Enable USART interrupt 3 ET1 Enable Timer1 interrupt 2 EX1 Enable external interrupt (Int1) 1 ET0 Enable Timer0 interrupt 0 EX0 Enable external interrupt (Int0) |
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