UPSD325X datasheet(85/176 Pages) STMICROELECTRONICS

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µPSD325X DEVICES

Table 61. Description of the DDCON Register Bits

Bit

Symbol

Function

—

Reserved

EX_DAT

0 = The SRAM has 128 bytes (Default)

1 = The SRAM has 256 bytes

5SWENB

Note: This bit is valid for DDC1 & DDC2b Modes

0 = Data is automatically read from SRAM at the current location of DDCADR and sent

out via current DDC protocol. (Default)

1 = MCU is interrupted during the current data byte transmission period to load the next

byte of data to send out.

DDC_AX

Note: This bit is valid for DDC1 & DDC2b Modes

0 = Data is automatically read from SRAM at the current location of DDCADR and sent

out via current DDC protocol. (Default)

1 = MCU is interrupted during the current data byte transmission period to load the next

byte of data to send out.

This bit only affects DDC2b Mode Operation:

0 = DDC2b I2C Address is A0/A1 (default)

1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored.

DDC1_Int

For DDC1 Mode Operation Only:

0 = No DDC1 interrupt

1 = DDC1 Interrupt request. Set by HW and should be cleared by SW interrupt service

routine.

Note1: This bit is set in the 9th VCLK at DDC1 Enable Mode. (SWENB=1)

DDC1EN

0 = DDC1 Mode is disabled – VSYNC is ignored.

The DDC unit will still respond to DDC2b requests. –provided I2C enabled.(Default)

1 = DDC1 Mode is enabled.

SWHINT

Set by hardware when the DDC unit switches from DDC1 to DDC2b Modes.

0 = No interrupt request.

1 = Switch to DDC2b Mode (Interrupt pending)

Set by HW and should be cleared by SW interrupt service routine.

Note1: This bit has no connection with SWENB.

0Mode

Current Mode Indication Bit:

0 = Unit is in DDC1 Mode

1 = Unit is in DDC2b Mode

Note: When the DDC unit transitions to DDC2b Mode, the DDC unit will stay in DDC2b

Mode until the DDC unit is disabled, or the system is reset.

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