UPSD325X datasheet(16/176 Pages) STMICROELECTRONICS

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µPSD325X DEVICES

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52 PIN PACKAGE I/O PORT

The 52-pin package members of the µPSD325X

devices have the same port pins as those of the

80-pin package except:

Port 0 (P0.0-P0.7, external address/data bus

AD0-AD7)

Port 2 (P2.0-P2.3, external address bus A8-

A11)

Port A (PA0-PA7)

Port D (PD2)

Bus control signal (RD,WR,PSEN,ALE)

Pin 5 requires a pull-up resistor (2k

Ω for 3V de-

vices, 7.5k

Ω for 5V devices) for all devices, with

or without USB function.

PB0

I/O

General I/O port pin

1. PLD Macro-cell outputs

2. PLD inputs

3. Latched Address Out (A0-A7)

PB1

I/O

General I/O port pin

PB2

I/O

General I/O port pin

PB3

I/O

General I/O port pin

PB4

I/O

General I/O port pin

PB5

I/O

General I/O port pin

PB6

I/O

General I/O port pin

PB7

I/O

General I/O port pin

PC0

TMS

JTAG pin

1. PLD Macro-cell outputs

2. PLD inputs

3. SRAM stand by voltage input

(VSTBY)

4. SRAM

battery-on

indicator

(PC4)

5. JTAG pins are dedicated pins

PC1

TCK

JTAG pin

PC2

VSTBY

I/O

General I/O port pin

PC3

TSTAT

I/O

General I/O port pin

PC4

TERR

I/O

General I/O port pin

PC5

TDI

JTAG pin

PC6

TDO

JTAG pin

PC7

I/O

General I/O port pin

PD1

CLKIN

I/O

General I/O port pin

1. PLD I/O

2. Clock input to PLD and APD

PD2

CSI

I/O

General I/O port pin

1. PLD I/O

2. Chip select to PSD Module

Vcc

GND

Port Pin

Signal

Name

Pin No.

In/Out

Function

Basic

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