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UPSD325X 数据表(PDF) 135 Page - STMicroelectronics |
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UPSD325X 数据表(HTML) 135 Page - STMicroelectronics |
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135 / 176 page ![]() 135/176 µPSD325X DEVICES External Chip Select The CPLD also provides two External Chip Select (ECS1-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS1-ECS2) consists of one product term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 68.) Figure 68. Port D External Chip Select Signals POLARITY BIT PD2 PIN PT2 ECS2 DIRECTION REGISTER ENABLE (.OE) POLARITY BIT PD1 PIN PT1 ECS1 ENABLE (.OE) DIRECTION REGISTER AI06607 |
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