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mit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de-

layed reverse mode.A separate MBIAS output can be used to bias a microphone (bit MB = 1 in register CR10)

1.1.5 Receive section:

Voice Data is shifted into the decoder's Receive voice data Register via the DR pin during the selected time slot

on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MCLK in non-

delayed reverse mode.

The decoder consists of either a 14-bit linear or an expanding DAC with A or MU255 law decoding characteristic.

Following the Decoder is a 3400 Hz 8th order band-pass switched capacitor filter with integral Sin X/X correction

for the 8 kHz sample and hold.

0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A transcient suppress-

ing circuitry ensure interference noise suppression at power up.

Total signal delay is approximatively 190

µs (filter plus decoding delay) plus 62.5µs (1/2 frame) which gives ap-

proximatively 252

µs.

Output VFR is intended to directly drive an earpiece. Preceding the outputs is a programmable attenuation am-

plifier, which must be set by writing to bits 4 to 7 in register CR6. Attenuations in the range 0 to -30 dB relative

to the maximum level in 2 dB step can be programmed. The input of this programmable amplifier is the sum of

several signals which can be selected by writing to register CR4.:

- Receive speech signal which has been decoded and filtered,

- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7),

- Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5

Ω load impedance capacitively connected

mable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range

0 to -30 dB relative to the maximum level in 2.0 dB step can be programmed. The input of this programmable

amplifier can be the sum of signals which can be selected by writing to register CR4:

- Receive speech signal which has been decoded and filtered,

- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7),

- Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5.

impedance of 8

Ω. Piezoceramic receivers up to 50nF can also be driven.

BUZZER OUTPUT:

Single ended output BZ is intended to drive a buzzer, via an external BJT, with a squarewave pulse width mod-

ulated (PWM) signal the frequency of which is stored into register CR8.

For some applications it is also possible to amplitude modulate this PWM signal with a squarewave signal hav-

ing a frequency stored in register CR9.

Maximum load for BZ is 5k

Ω and 50pF.

1.1.6 Digital Interface (Fig. 1)

to a squarewave. Three different relationships may be established between the Frame Sync input and the first

time slot of frame by setting bits DM1 and DM0 in register CR1. In non delayed data mode (long frame timing)

(short frame sync timing) in which FS input must be high at least a half cycle of MCLK earlier the frame beginning

In the case of linear code (bit CM = 0 in register CR0) the MSB is the first bit that is transmitted and received.