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STW5093

In the case of companded code only (bit CM = 1 in register CR0) a time slot assignment circuit on chip may be

used with all timing modes, allowing connection to one of the two B1 and B2 voice data channels.

Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles following immedi-

ately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles following immediately time slot

B1.

In Format 2, time slot B1 is identical to Format 1. Time slot B2 appears two bit slots after time slot B1. This two

bits space is left available for insertion of the D channel data.

Data format is selected by bit FF (2) in register CR0. Time slot B1 or B2 is selected by bit TS (1) in Control Reg-

ister CR1.

ing the assigned time slot, DX output shifts data out from the voice data register on the rising edges of MCLK

in the case of delayed and non-delayed normal modes or on the falling edges of MCLK in the case of non-de-

layed reverse mode. Serial voice data is shifted into DR input during the same time slot on the falling edges of

MCLK in the case of delayed and non-delayed normal modes or on the rising edges of MCLK in the case of non-

delayed reverse mode.

Figure 1. Digital Interface Format (significant only for companded code)

1.1.7 Control Interface:

Control information or data is written into or read-back from STw5093 via the serial control port consisting of

control clock CCLK, serial data input CI and output CO, and Chip Select input, CS-. All control instructions re-

quire 2 bytes as listed in Table 1, with the exception of a single byte power-up/down command.

To shift control data into STw5093, CCLK must be pulsed high 8 times while CS- is low. Data on CI input is

shifted into the serial input register on the rising edge of each CCLK pulse. After all data is shifted in, the content

of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow. This second

byte may either be defined by a second byte-wide CS- pulse or may follow the first contiguously, i.e. it is not

mandatory for CS- to return high in between the first and second control bytes. At the end of the 2nd control

byte, data is loaded into the appropriate programmable register. CS- must return high at the end of the 2nd byte.

(non delayed timing)

(delayed timing)

FS

FS

X

B2

B1

XX

B2

B1

MCLK

DR

DX

FORMAT 1

(non delayed timing)

(delayed timing)

FS

FS

X

B2

B1

XX

B2

B1

MCLK

DR

DX

FORMAT 2

D98TL394