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STW5093 数据表(PDF) 15 Page - STMicroelectronics

部件名 STW5093
功能描述  2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
PDF  34 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STW5093 数据表(HTML) 15 Page - STMicroelectronics

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STW5093
Latch output control
Bit DO controls directly logical status of latch output LO: ie, a "ZERO" written in bit DO puts the output LO at
logical 1, while a "ONE" written in bit DO sets the output LO to zero.
Microwire access to B channel on receive path (1)
Bit MR (4) selects access from MICROWIRE Register CR2 to Receive path. When bit MR is set high, data writ-
ten to register CR2 is decoded each frame, sent to the receive path and data input at DR is ignored.
In the other direction, current PCM data input received at DR can be read from register CR2 each frame.
Microwire access to B channel on transmit path (1)
Bit MX (3) selects access from MICROWIRE write only Register CR3 to DX output. When bit MX is set high,
data written to CR3 is output at DX every frame and the output of PCM encoder is ignored.
MSB is always the first PCM bit shifted in or out of: STw5093.
Transmit/Receive enabling/disabling
Bit 'EN' (2) enables or disables voice data transfer on DX and DR pins. When disabled, PCM data from DR is
not decoded and PCM time-slots are high impedance on DX. Default value is disabled.
B-channel selection (1)
Bit TS(1) permits selection between B1 or B2 channels. Default value is B1 channel.
Clock Selection
Bit SLC(0) allows the selection between MCLK and AUXCLK. Default value is MCLK.
CONTROL REGISTER CR2(1)
Data sent to receive path or data received from DR input. Refer to bit MR(4) in "Control Register CR1" para-
graph.
CONTROL REGISTER CR3 (1)
DX data transmitted. Refer to bit MX(3) in "Control Register CR1" paragraph.
CONTROL REGISTER CR4
First byte of a READ or a WRITE instruction to Control Register CR4 is as shown in TABLE 1. Second byte is
as shown in TABLE 6.
(1) Significant in companded mode only
Mu 255 law
True A law even bit
inversion
A law without even bit
inversion
msb
lsb
msb
lsb
msb
lsb
Vin = + full scale
1000
000
01
01010101
1111111
Vin = 0V
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Vin = - full scale
0000
000
00
01010100
1111111



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