STw5093

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24

VCCIO

Power supply Input for the Digital I/O's.

25

CO

Control data Output: Serial control/status information is shifted out from the STw5093 on this pin

when CS- is low on the falling edges of CCLK.

26

GND

Ground: All digital signals are referenced to this pin.

27

Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots.

Elsewhere DX output is in the high impedance state. In delayed and non-delayed normal frame

synchr. modes, voice data byte is shifted out from TRISTATE output DX at the MCLK on the

rising edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted

out on the falling edge of MCLK.

28

Receive data input: Data is shifted in during the assigned Received time slots In delayed and

non-delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on

the falling edges of MCLK, while in non-delayed reverse frame synchr. mode voice data byte is

shifted in at the MCLK frequency on the rising edges of MCLK.

29

FS

Frame Sync input: This signal is a 8kHz clock which defines the start of the transmit and receive

frames. Any of three formats may be used for this signal: non delayed normal mode, delayed

mode, and non delayed reverse mode.

30

MCLK

Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder

sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by

means of Control Register CR0. MCLK is used also to shift-in and out data.

N°

Pin

Description

PIN FUNCTION (continued)