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STW5093 数据表(PDF) 3 Page - STMicroelectronics |
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STW5093 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 34 page ![]() 3/34 STW5093 PIN FUNCTION N° Pin Description 1VCC Power supply input for the digital section. 2 REMOUT Remocon function digital output. 3 REMIN Remocon function input. An high level at this pin is detected as a non pressed key, while a low level is detected as a pressed key. 4 MIC3+ Third positive high impedance input to transmit preamplifier for microphone connection. 5 MIC3- Third negative high impedance input to transmit preamplifier for microphone connection. 6 MBIAS Microphone Biasing Switch. 7VCCA Power supply input for the analog section. VCC and VCCA can be directly connected together for low cost applications (see STw5093 Power Supply Notes). 8 MIC1+ Positive high impedance input to transmit pre-amplifier for microphone connection. 9 MIC1- Negative high impedance input to transmit pre-amplifier for microphone connection. 10 GNDA Analog Ground: All analog signals are referenced to this pin. GND and GNDA can be connected together for low cost applications (see STw5093 Power Supply Notes). 11 MIC2+ Second Positive high impedance input to transmit pre-amplifier for microphone connection. 12 MIC2- Second negative high impedance input to transmit pre-amplifier for microphone connection. 13 VCCP Power supply input for the VFr and VLr drivers. VCCP and VCCA must be connected together. 14,15 VLr-, VLr+ Receive analog extra amplifier complementary outputs. These outputs can drive directly earpiece transductor of 8 Ω or 50nF. The signal at these outputs can be the sum of: - Receive Speech signal from DR, - Internal Tone generator, - Sidetone signal. 16 GNDP Power ground. VFr and VLr drivers are referenced to this pin. GNDP and GNDA must be connected together. 17 VFr Receive analog earpiece amplifier output. This output can drive directly earpiece transductor of 30 Ω or 50nF. The signal at this output can be the sum of: - Receive Speech signal from DR, - Internal Tone Generator, - Sidetone signal. 18 LO A logic 1 written into DO (CR1) appears at LO pin as a logic 0 A logic 0 written into DO (CR1) appears at LO pin as a logic 1. 19 BZ Pulse width modulated buzzer driver output. 20 CCLK Control Clock input: This clock shifts serial control information into CI and out from CO when the CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 21 CS- Chip Select input: When this pin is low, control information is written into and out from the STw5093 via CI and CO pins. 22 CI Control data Input: Serial Control information is shifted into the STw5093 on this pin when CS- is low on the rising edges of CCLK. 23 AUXCLK Auxiliary Clock Input. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CR0. AUXCLK is not used to shift in and out data |
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