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STW5093

1.0 FUNCTIONAL DESCRIPTION

1.1 DEVICE OPERATION

1.1.1 Power on initialization:

When power is first applied, power on reset circuitry initializes STw5093 and puts it into the power down state.

Gain Control Registers for the various programmable gain amplifiers and programmable switches are initialized

as indicated in the Control Register description section. All CODEC functions are disabled.

The desired selection for all programmable functions may be intialized prior to a power up command using the

MICROWIRE control channel.

Note: after register programming, a subsequent activation of the internal Power on Reset can be detected by

programming to 1 the DO bit in the CR1 register; this sets to the logic level 0 the LO output. If an internal Power

on Reset occurs, LO automatically switches to logic level 1.

1.1.2 Power up/down control:

Following power-on initialization, power up and power down control may be accomplished by writing any of the

control instructions listed in Table 1 into STw5093 with "P" bit set to 0 for power up or 1 for power down.

Normally, it is recommended that all programmable functions be initially programmed while the device is pow-

ered down. Power state control can then be included with the last programming instruction or in a separate sin-

gle byte instruction.

Any of the programmable registers may also be modified while STw5093 is powered up or down by setting "P"

bit as indicated. When power up or down control is entered as a single byte instruction, bit 1 must be set to a 0.

When a power up command is given, all de-activated circuits are activated, but output DX will remain in the high

impedance state until the second Fs pulse after power up.

1.1.3 Power down state:

Following a period of activity, power down state may be reentered by writing a power down instruction.

Control Registers remain in their current state and can be changed by MICROWIRE control interface.

In addition to the power down instruction, detection of loss MCLK (no transition detected) automatically enters

the device in "reset" power down state with DX output in the high impedance state.

1.1.4 Transmit section:

Transmit analog interface is designed in two stages to enable gains up to 42.5 dB to be realized. Stage 1 is a

low noise differential amplifier providing a selectable 0 or 20 dB gain via bit 1 (PG) of register CR4. A microphone

may be capacitevely connected to MIC1+, MIC1- inputs, while the MIC2+ MIC2Ä and MIC3+ MIC3- inputs may

be used to capacitively connect a second microphone or a third microphone respectively or an auxiliary audio

circuit. MIC1 or MIC2 or MC3 or transmit mute is selected with bits 6 and 7 of register CR4.

In the mute case, the analog transmit signal is grounded and the sidetone path is also disabled. Following the

first stage is a programmable gain amplifier which provides from 0 to 22.5 dB of additional gain in 1.5dB step.

The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the in-

ternal 0 dBm0 voltage is 0.49 Vrms (overload level is 0.7 Vrms). Second stage amplifier gain can be pro-

grammed with bits 4 to 7 of CR5.

An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter can be

either a 14-bit linear (bit CM = 0 in register CR0) or can have a compressing characteristics (bit CM = 1 in reg-

ister CR0) according to CCITT A or MU255 coding laws. A precision on chip voltage reference ensures accurate

and highly stable transmission levels.

Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an internal au-

tozero circuit.

Each encode cycle begins immediatly at the beginning of the selected Transmit time slot. The total signal delay

referenced to the start of the time slot is approximatively 195

µs (due to the transmit filter) plus 125 µs (due to

encoding delay), which totals 320

µs. Voice data is shifted out on DX during the selected time slot on the trans-