STw5093

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CONTROL REGISTER CR0

First byte of a READ or a WRITE instruction to Control Register CR0 is as shown in TABLE 1.

Second byte is as shown in TABLE 2.

Master Clock / Auxiliary Clock Frequency Selection

A master clock must be provided to STw5093 to activate all the functions. In the case MCLK is absent, AUXCLK

can be provide to STw5093 for activating tone or buzzer functions only.

MCLK or AUXCLK frequency can be either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz..

Bit F1 (7) and F0 (6) must be set during initialization to select the correct internal divider.Default value is 512

kHz. Any clock different from the default one must be selected prior a Power-Up instruction.

Coding Law Selection

Bits MA (4) and IA (3) permit selection of Mu-255 law or A law coding with or without even bit inversion if com-

panded code (bit CM = 1) is selected. Bits MA(4) and IA(3) permit selection of 2-complement, 1-complement or

sign and magnitude if linear code (bit CM = 0) is selected.

Coding Selection

Bit CM (5) permits selection either of linear coding (14-bit) or companded coding (8-bit). Default value is linear

coding.

Digital Interface format (1)

Bit FF(2) = 0 selects digital interface in Format 1 where B1 and B2 channel are consecutive. FF=1 selects For-

mat 2 where B1 and B2 channel are separated by two bits. (See digital interface format section.)

56+8 selection (1)

Bit 'B7' (1) selects capability for STw5093 to take into account only the seven most significant bits of the PCM

data byte selected.

When 'B7' is set, the LSB bit on DR is ignored and LSB bit on DX is high impedance. This function allows con-

nection of an external "in band" data generator directly connected on the Digital Interface.

Digital loopback

Digital loopback mode is entered by setting DL bit(0) equal 1.

In Digital Loopback mode, data written into Receive PCM Data Register from the selected received time-slot is

No PCM decoding or encoding takes place in this mode. Transmit and Receive amplifier stages are muted.

CONTROL REGISTER CR1

First byte of a READ or a WRITE instruction to Control Register CR1 is as shown in TABLE 1. Second byte is

as shown in TABLE 3.

Digital Interface Timing

Bit DM1(7) = 0 selects digital interface in delayed timing mode, while DM1 = 1 and DM0 = 0 selects non-delayed

normal data timing mode, and DM1 = 1 and DM0 = 1 selects non-delayed reverse data timing mode.Default is

delayed data timing.

(1) Significant in companded mode only