4

Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial

data input (D) is sampled on the first rising edge of the Serial clock (C) after Chip select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial data output (Q) is latched on

the first falling edge of the Serial clock (C) after the instruction (such as the Read from Memory array and Read

Status register instructions) have been clocked into the device.

Figure 5. Bus master and memory devices on the SPI bus

SPI bus master

SDO

SDI

SCK

C Q D

C Q D

C Q D

CS3 CS2 CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or 1, 1)

SPI memory

device

S W HOLD

R

R

R

SPI memory

device

S W HOLD

SPI memory

device

S W HOLD

VCC

VCC

VCC

VCC

VSS

(1)

(1)

(1)

(1)

(1)

(1)

1. The Write protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

MS19755V3

Figure 5 shows an example of three memory devices connected to an SPI bus master. Only one memory device

is selected at a given time, so only one memory device drives the Serial data output (Q) line at that time. The

other memory devices are in high impedance state. The pull-up resistor R ensures that a device is not selected if

the Bus master leaves the S line in the high impedance state.

In applications where the bus master can enter a state where the whole input/output SPI bus is high-impedance

at a given time (for example, if the bus master is reset during the transmission of an instruction), it is advised to

connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high-impedance,

the C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the

same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.

M95256-W M95256-R M95256-DF

Connecting to the SPI bus

DS4712 - Rev 22

page 6/51