M95256-DF datasheet(19/51 Pages) STMICROELECTRONICS

19 / 51 page

6.6

Write to Memory array (WRITE)

As shown in Figure 13, to send this instruction to the device, Chip select (S) is first driven low. The bits of the

instruction byte, address byte, and at least one data byte are then shifted in, on Serial data input (D).

The instruction is terminated by driving Chip select (S) high at a byte boundary of the input data. The self

‑timed

Write cycle, triggered by the Chip select (S) rising edge, continues for a period tW (as specified in AC

characteristics in Section 9 DC and AC parameters), at the end of which the Write in Progress (WIP) bit is

reset to 0.

Figure 13. Byte Write (WRITE) sequence

3 4 5 6 7 8 9 10

20 21 22 23 24 25 26 27

14 13

3 2 1 0

28 29 30

High impedance

Instruction

16-bit address

7 6 5 4 3 2

Data byte

Note:

Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most

significant address bits are Don’t care.

In the case of Figure 13, Chip select (S) is driven high after the eighth bit of the data byte has been latched

in, indicating that the instruction is being used to write a single byte. However, if Chip select (S) continues to

be driven low (as shown in Figure 14), the next byte of input data is shifted in, so that more than a single byte,

starting from the given address towards the end of the same page, can be written in a single internal Write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented.

If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of

roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page.

The instruction is not accepted, and is not executed, under the following conditions:

•

if the Write enable latch (WEL) bit has not been set to 1 (by executing a Write enable instruction just before),

•

if a Write cycle is already in progress,

•

if the device has not been deselected, by driving high Chip select (S), at a byte boundary (after the eighth

bit, b0, of the last data byte that has been latched in),

•

if the addressed page is in the region protected by the Block protect (BP1 and BP0) bits.

Note:

The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed

byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as

“1”.

M95256-W M95256-R M95256-DF

Write to Memory array (WRITE)

DS4712 - Rev 22

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