7

AT49LL080

3273C–FLASH–5/03

START: This one-clock field indicates the start of a cycle. It is valid on the last clock that

LFRAME is sampled low. On the rising edge of CLK with LFRAME low, the contents of

LAD3 - LAD0 must be 0000b to indicate the start of a LPC cycle.

CYCTYPES + DIR: This one-clock field is used to indicate the type of cycle and direc-

tion of transfer. Bits 3 - 2 must be “01b” for a memory cycle. Bit 1 indicates the type of

transfer: “0” for read operation, “1” for write operation. DIR field indication of transfer: “0”

for read, “1” for write. Bit 0 is reserved. “010xb” indicates a memory read cycle; while

“011xb” indicates a memory write cycle.

MADDR (MEMORY ADDRESS): This is an eight-clock field, which gives a 32-bit mem-

ory address. LPC supports the 32-bit address protocol. The address is transferred with

the most significant nibble first. For the AT49LL080, address bit 23 directs Reads and

TURN-AROUND (TAR): This field is two clocks wide, and is driven by the master when

it is turning control over to the LPC, (for example, to read data), and is driven by the LPC

when it is turning control back over to the master. On the first clock of this two-clock-

wide field, the master or LPC drives the LAD[3:0] lines to “1111b”. On the second clock

of this field, the master or peripheral tri-states the LAD[3:0] lines.

SYNC: This field is used to add wait states. It can be several clocks in length. On target

or DMA cycles, this field is driven by the LPC. If the LPC needs to assert wait states, it

does so by driving “0101b” (short SYNC) on LAD[3:0] until it is ready. When ready, it will

drive “0000b”. Valid values for this field are shown in Table 4.

Table 3. CYCTYPE + DIR Fields

LAD[3:0]

Indication

010xb

LPC Memory Read

011xb

LPC Memory Write

Table 4. Valid SYNC Values

Bits[3:0]

Indication

0000

Ready: SYNC achieved with no error.

0101

Short Wait: Part indicating wait states.