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AT49LL080

3273C–FLASH–5/03

GPI[4:0]

INPUT

GENERAL PURPOSE INPUTS: These individual inputs can be used for

additional board flexibility. The state of these pins can be read through LPC

registers. These inputs should be at their desired state before the start of the

PCI clock cycle during which the read is attempted, and should remain at the

same level until the end of the read cycle. They may only be used for 3.3V

signals. Unused GPI pins must not be floated.

A/A Mux = A[10:6]

TBL

INPUT

TOP SECTOR LOCK: When low, prevents programming or sector erase to the

highest addressable sector (15), regardless of the state of the lock registers

TBL high disables hardware write protection for the top sector, though register-

based protection still applies. The status of TBL does not affect the status of

sector-locking registers.

A/A Mux = A4

INPUT

WRITE-PROTECT: When low, prevents programming or sector erase to all but

the highest addressable sectors (0 - 14), regardless of the state of the

corresponding lock registers. WP-high disables hardware write protection for

these sectors, though register-based protection still applies. The status of TBL

does not affect the status of sector-locking registers.

A/A Mux = A5

A0 - A10

INPUT

LOW-ORDER ADDRESS INPUTS: Inputs for low-order addresses during read

and write operations. Addresses are internally latched during a write cycle. For

the A/A Mux interface these addresses are latched by R/C and share the same

pins as the high-order address inputs.

I/O0 - I/O7

I/O

DATA INPUT/OUTPUTS: These pins receive data and commands during write

cycles and transmit data during memory array and identifier code read cycles.

Data pins float to high-impedance when the chip is deselected or outputs are

disabled. Data is internally latched during a write cycle.

INPUT

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

R/C

INPUT

ROW-COLUMN ADDRESS SELECT: For the A/A Mux interface, this pin

determines whether the address pins are pointing to the row addresses,

A0 - A10, or to the column addresses, A11 - A19.

INPUT

WRITE ENABLE: Controls writes to the array sectors. Addresses and data are

latched on the rising edge of the WE pulse.

SUPPLY

SECTOR ERASE/PROGRAM POWER SUPPLY: For erasing array sectors or

programming data 0V < V

PP < 3.6V or 12V for faster erase and programming

operations. The VPP pin can be left unconnected. Sector erase or program with

an invalid V

PP (see DC Characteristics) produces spurious results and should

not be attempted. V

PP may only be held at 12V for 80 hours over the lifetime of

the device.

SUPPLY

DEVICE POWER SUPPLY: Internal detection automatically configures the

device for optimized read performance. Do no float any power pins. With V

CC ≤

LKO, all write attempts to the flash memory are inhibited. Device operations at

invalid V

CC voltages (see DC Characteristics) produce spurious results and

should not be attempted.

GND

SUPPLY

GROUND: Do not float any ground pins.

CCa

SUPPLY

ANALOG POWER SUPPLY: This supply should share the same system supply

as V

CC.

Table 1. Pin Description (Continued)

Symbol

Type

Interface

Name and Function

LPC

A/A Mux

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