6

AT49LL080

3273C–FLASH–5/03

internal circuits. RST or INIT must be held low for time t

tion). The LPC resets to read array mode upon return from reset, and all sectors are set

to default (locked) status regardless of their locked state prior to reset.

Driving RST or INIT low resets the device, which resets the sector lock registers to their

default (write-locked) condition. A reset time (t

INIT switching high until outputs are valid. Likewise, the device has a wake time (t

PHRH

A/A Mux) from RST or INIT high until writes to the CUI are recognized. A reset latency

will occur if a reset procedure is performed during a programming or erase operation.

During sector erase or program, driving RST or INIT low will abort the operation under-

way, in addition to causing a reset latency. Memory contents being altered are no longer

valid, since the data may be partially erased or programmed.

It is important to assert RST or INIT during system reset. When the system comes out of

reset, it will expect to read from the memory array of the device. If a system reset occurs

with no LPC reset (this will be hardware dependent), it is possible that proper CPU ini-

tialization will not occur (the LPC memory may be providing status information instead of

memory array data).

CYCLE TYPES: There are two types of cycles that are supported by the AT49LL080:

LPC Memory Read and LPC Memory Write.

Device Operation

READ: Read operations consist of START, CYCTYPE + DIR, ADDRESS, TAR, SYNC

and data fields as shown in Figure 1 and described in Table 5. The different fields are

described below. Commands using the read mode include the following functions: read-

ing memory from the array, reading the identifier codes, reading the lock bit registers

and reading the GPI registers. Memory information, identifier codes, or the GPI registers

can be read independent of the V

from reset mode, the device automatically resets to read array mode.

READ CYCLE, SINGLE BYTE: For read cycles, after the address is transferred, the

master drives a TAR field to give ownership of the bus to the LPC. After the second

clock of the TAR phase the LPC assumes the bus and begins driving SYNC values.

When it is ready, it drives the low nibble, then the high nibble of data, followed by a TAR

field to give control back to the master.

Figure 1 shows a device that requires three SYNC clocks to access data. Since the

access time can begin once the address phase has been completed, the two clocks of

the TAR phase can be considered as part of the access time of the part. For example, a

device with a 120 ns access time could assert “0101b” for clocks 1 and 2 of the SYNC

phase and “0000b” for the last clock of the SYNC phase. This would be equivalent to

five clocks worth of access time if the device started that access at the conclusion of the

preamble phase. Once SYNC is achieved, the device then returns the data in two clocks

and gives ownership of the bus back to the master with a TAR phase.