3

AT49LL080

3273C–FLASH–5/03

Pin Description

Table 1 details the usage of each of the device pins. Most of the pins have dual function-

ality, with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux

functionality for pins is shown in bold in the description box for that pin. All pins are

designed to be compliant with voltage of V

Table 1. Pin Description

Symbol

Type

Interface

Name and Function

LPC

A/A Mux

IC

INPUT

X

X

INTERFACE CONFIGURATION PIN: This pin determines which interface is

operational. This pin is held high to enable the A/A Mux interface. This pin is

held low to enable the LPC interface. This pin must be set at power-up or before

return from reset and not changed during device operation. This pin is pulled

down with an internal resistor, with values between 20 and 100 k

Ω. With IC high

(A/A Mux mode), this pin will exhibit a leakage current of approximately 200 µA.

This pin may be floated, which will select LPC mode.

RST

INPUT

X

X

INTERFACE RESET: Valid for both A/A Mux and LPC interface operations.

When driven low, RST inhibits write operations to provide data protection during

power transitions, resets internal automation, and tri-states pins LAD[3:0] (in

LPC interface mode). RST high enables normal operation. When exiting from

reset, the device defaults to read array mode.

INIT

INPUT

X

PROCESSOR RESET: This is a second reset pin for in-system use. This pin is

internally combined with the RST pin. If this pin or RST is driven low, identical

operation is exhibited. This signal is designed to be connected to the chipset

INIT signal (Max voltage depends on the processor. Do not use 3.3V.)

A/A Mux = OE

CLK

INPUT

X

33 MHz CLOCK for LPC INTERFACE: This input is the same as the PCI clock

and adheres to the PCI specification.

A/A Mux = R/C

LAD[3:0]

I/O

X

ADDRESS AND DATA: These pins provide LPC control signals, as well as

addresses and command Inputs/Outputs Data.

A/A Mux = I/O[3:0]

LFRAME

INPUT

X

FRAME: This pin indicates the start of a data transfer operation; also used to

abort an LPC cycle in progress.

A/A Mux = WE

ID[3:1]

INPUT

X

IDENTIFICATION INPUTS: These three pins are part of the mechanism that

allows multiple parts to be attached to the same bus. The strapping of these

pins is used to identify the component. The boot device must have ID[3:1] =

000, and it is recommended that all subsequent devices should use a

sequential up-count strapping (i.e., 001, 010, 011, etc.). These pins are pulled

down with internal resistors, with values between 20 and 100 k

Ω when in LPC

mode. Any ID pins that are pulled high will exhibit a leakage current of

approximately 200 µA. Any pins intended to be low may be left to float. In a

single LPC system, all may be left floating.

A/A Mux = A[3:0]

CE

INPUT

X

When CE is low, the device is enabled. This pin is pulled down with an

internal resistor and can exhibit a leakage current of approximately 10 µA.

Since this pin is internally pulled down and thus can be left unconnected, the

AT49LL080 is compatible with systems that do not use a CE signal. To reduce

power, the device is placed in a low-power standby mode when CE is high.