13

AT49LL080

3273C–FLASH–5/03

Note:

1. The Write Lock bit must be set to the desired protection state prior to starting a program or erase operation since it is sam-

pled at the beginning of the operation. Changing the state of the Write Lock bit during a program or erase operation may

cause unpredictable results. If the state of the Write Lock bit changes during a program suspend or erase suspend state, the

changes to the sector’s locking status do not take place immediately. The suspended operation may be resumed success-

fully. The new lock status will take place after the program or erase operation completes. The individual bit functions are

described in the following sections.

READ LOCK: The default read status of all sectors upon power-up is read-unlocked.

When a sector’s read-lock bit is set (1 state), data cannot be read from that sector. An

attempted read from a read-locked sector will result in data 00H being read. (Note that

failure is not reflected in the status register). The read-lock status can be unlocked by

clearing (0 state) the read-lock bit, provided the lock-down bit has not been set. The cur-

rent read-lock status of a particular sector can be determined by reading the

corresponding read-lock bit.

WRITE LOCK: The default write status of all sectors upon power-up is write-locked

(1 state). Any program or erase operations attempted on a locked sector will return an

error in the status register (indicating sector lock). The status of the locked sector can be

changed to unlocked (0 state) by clearing the write-lock bit, provided the lock-down bit is

not also set. The current write-lock status of a particular sector can be determined by

reading the corresponding write-lock bit. Any program or erase operations attempted on

a locked sector will return an error in the status register (indicating sector lock). The

write-lock functions in conjunction with the hardware write-lock pins, TBL and WP.

When active, these pins take precedence over the register-locking function and write-

lock the top sector or remaining sectors, respectively. Reading this register will not read

the state of the TBL or WP pins.

LOCK-DOWN: When in the LPC interface mode, the default lock-down status of all sec-

tors upon power-up is not-locked-down (0 state). The lock-down bit for any sector may

be set (1 state), but only once, as future attempted changes to that sector locking regis-

ter will be ignored. The lock-down bit is only cleared upon a device reset with RST or

INIT. The current lock-down status of a particular sector can be determined by reading

the corresponding lock-down bit. Once a sector’s lock-down bit is set, the read- and

write-lock bits for that sector can no longer be modified and the sector is locked down in

its current state of read and write accessibility.

GENERAL-PURPOSE INPUTS REGISTER: This register reads the status of the

GPI[4:0] pins on the LPC at power-up. Since this is a pass-through register, there is no

default value as shown in Table 7. It is recommended that the GPI pins be in the desired

state before LFRAME is brought low for the beginning of the next bus cycle, and remain

in that state until the end of the cycle.

Table 9. Register-based Locking Value Definitions

Data

Reserved

Data 7 - 3

Read Lock,

Data 2

Lock-down,

Data 1

Write Lock,

Data 0

Resulting Sector State

(1)

00

00000

00

0

Full access

01

00000

00

1

Write locked – Default state at power-up

02

00000

01

0

Locked open (full access locked down)

03

00000

01

1

Write locked down

04

00000

10

0

Read locked

05

00000

10

1

Read and write locked

06

00000

11

0

Read locked down

07

00000

11

1

Read and write locked down