18

AT49LL080

3273C–FLASH–5/03

BUS OPERATION: All A/A Mux bus cycles can be conformed to operate on most auto-

mated test equipment and PROM programmers.

Notes:

1. X can be V

2. See Table 11 on page 15 for Product ID Entry data and addresses.

3. Command writes involving sector erase or program are reliably executed when V

4. Refer to “A/A Mux Read-only Operations” for valid D

5. V

OUTPUT DISABLE/ENABLE: With OE at a logic-high level (V

disabled. Output pins I/O0 - I/O7 are placed in the high-impedance state. With OE at a

logic-low level (V

in a output-drive state.

ROW/COLUMN ADDRESSES: R/C is the A/A Mux control pin used to latch row (A0 -

A10) and column addresses (A11 - A19). R/C latches row addresses on the falling edge

and column addresses on the rising edge.

RDY/BUSY: An open drain Ready/Busy output pin provides a hardware method of

detecting the end of a program or erase operation. RDY/Busy is actively pulled low dur-

ing the internal program and erase cycles and is released at the completion of the cycle.

Bus Operations

Mode

RST

OE

WE

Address

I/O0 - I/O7

Read

(1)(5)

V

IH

V

IL

V

IH

XX

D

OUT

Output Disable

(5)

V

IH

V

IH

V

IH

X

X

High-Z

Product ID Entry

(5)

(2)

XNote 3

Write

(3)(4)(5)

V

IH

V

IH

V

IL

XX

D

IN