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STM32G0C1NET3 数据表(PDF) 104 Page - STMicroelectronics |
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STM32G0C1NET3 数据表(HTML) 104 Page - STMicroelectronics |
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104 / 159 page  Electrical characteristics STM32G0C1xC/xE 104/159 DS13564 Rev 4 8 bits 1.5(3) 43 82 3.5 100 1500 7.5 214 3900 12.5 357 6800 19.5 557 12000 39.5 1129 27000 79.5 2271 50000 160.5 4586 50000 6 bits 1.5(3) 43 390 3.5 100 2200 7.5 214 5600 12.5 357 10000 19.5 557 15000 39.5 1129 33000 79.5 2271 50000 160.5 4586 50000 1. Guaranteed by design. 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 3. Only allowed with VDDA > 2 V Table 62. Maximum ADC RAIN . (continued) Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN(1)(2) (Ω) Table 63. ADC accuracy(1)(2)(3) Symbol Parameter Conditions(4) Min Typ Max Unit ET Total unadjusted error VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C -3 4 LSB 2 V < VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -3 6.5 1.65 V < VDDA=VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; -3 7.5 |
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