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STM32G0C1NET3 数据表(PDF) 109 Page - STMicroelectronics

部件名 STM32G0C1NET3
功能描述  Arm® Cortex®-M0 32-bit MCU, up to 512KB Flash, 144KB RAM,6x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V
PDF  159 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32G0C1NET3 数据表(HTML) 109 Page - STMicroelectronics

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DS13564 Rev 4
109/159
STM32G0C1xC/xE
Electrical characteristics
124
TW_to_W
Minimum time between two
consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
DAC_MCR:MODEx[2:0] = 000 or
001
CL ≤ 50 pF; RL ≥ 5 kΩ
1-
-
µs
DAC_MCR:MODEx[2:0] = 010 or
011
CL ≤ 10 pF
1.4
-
-
tSAMP
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
DAC_OUT
pin connected
DAC output buffer
ON, CSH = 100 nF
-0.7
3.5
ms
DAC output buffer
OFF, CSH = 100 nF
-10.5
18
DAC_OUT
pin not
connected
(internal
connection
only)
DAC output buffer
OFF
-2
3.5
µs
Ileak
Output leakage current
Sample and hold mode,
DAC_OUT pin connected
--
-(3)
nA
CIint
Internal sample and hold
capacitor
-
5.2
7
8.8
pF
tTRIM
Middle code offset trim time DAC output buffer ON
50
-
-
µs
Voffset
Middle code offset for 1 trim
code step
VREF+ = 3.6 V
-
1500
-
µV
VREF+ = 1.8 V
-
750
-
IDDA(DAC)
DAC consumption from
VDDA
DAC output
buffer ON
No load, middle
code (0x800)
-
315
500
µA
No load, worst code
(0xF1C)
-
450
670
DAC output
buffer OFF
No load, middle
code (0x800)
--
0.2
Sample and hold mode, CSH =
100 nF
-
315 ₓ
Ton/(Ton+
Toff)(4)
670 ₓ
Ton/(Ton+
Toff)(4)
Table 64. DAC characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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