SAF784X datasheet(21/93 Pages) NXP

21 / 93 page

SAF784X_2

Product data sheet

Rev. 02 — 9 May 2008

21 of 93

NXP Semiconductors

SAF784x

One chip CD audio device with integrated MP3/WMA decoder

For the application, it should be noted that the interface supports 32-bit registers, while the

decoder only contains 8-bit registers. Therefore, the decoder registers are treated as

32-bit registers of which the 24 MSBs are not used.

The register address map occupied by the decoder goes from relative address

0x3000 0000 to address 0x3000 0374, and can be split into two parts:

0x3000 0000 - 0x3000 024C: the decoder’s own registers - used to conﬁgure the

channel decoder, and the functionality they control is described in detail in this section.

0x3000 02A0 - 0x3000 0374: the decoder immigrant registers - used to control parts of

the SAF784x that do not have their own AHB interface (they are not used to control the

decoder channel decoder).

6.5.4.2

Interrupt strategy

The channel decoder contains two interrupt status registers: InterruptStatus1 contains all

interrupts that operate as set/reset latches (set by hardware, reset by reading from the

hardware, reset by hardware or by accessing other registers).

Each interrupt bit can be enabled or disabled separately by writing to its corresponding

enable bit in the InterruptEnable1 and InterruptEnable2 registers. If one or several

interrupt bits are set and at least one is enabled, the interrupt line of the decoder to the

microcontroller will go active (LOW). If an interrupt bit is disabled (enable bit turned off), it

is prevented from activating the interrupt line to the microcontroller. However, this mode

allows the interrupt to be processed if the status register is polled instead of interrupt

handling by the microcontroller.

6.5.5 EFM bit detection and demodulation

A block diagram of the bit recovery is shown in Figure 10.

The HF signal comprises the four diode inputs inside the analog block. It is pre-processed

(LPF, HPF, offset removal and gain adjustment) and then sampled by a 6-bit ADC.

On the sampled HF, bit recovery is done by means of a full digital PLL and slicer.

Before the sampled signal enters the PLL section, it is pre-processed by a signal

conditioning block. This consists of an integrate-and-dump block, a high-pass ﬁlter and

logic available for gain control and offset control on the RF signal in the analog section.

For good playability on defects, a defect detector puts the PLL, the slicer, the AGC, the

offset cancellation and the high-pass ﬁlter into hold during defects.

Fig 10. Bit recovery block diagram

001aag314

to demodulator

AGC

AOC

SIGNAL

CONDITIONING

BLOCK

6-bit

ADC

ANALOG

BLOCK

PLL AND

BIT SLICER

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