SAF784X datasheet(12/93 Pages) NXP

12 / 93 page

SAF784X_2

Product data sheet

Rev. 02 — 9 May 2008

12 of 93

NXP Semiconductors

SAF784x

One chip CD audio device with integrated MP3/WMA decoder

To help users set up the correct gain and DC offset for each particular mechanism, an eye

pattern monitor facility is included. This consists of a high frequency buffer ampliﬁer

whose input can be selected to monitor various important nodes within the analog RF

path. The monitor point is controlled by register RFControl1[6:4] ﬁeld RFMONSEL. The

output of the buffer drives HF_MON pin (pin 7). This register also controls the roll-off

frequency of the noise ﬁlter which is in front of the 6-bit ADC in the RF path.

Various blocks within the analog RF path can be powered down if required, including the

complete path. These power-down bits are controlled by register RFControl2[5:0].

In addition, the 6-bit RF ADC can be stand-alone tested in application mode, or a separate

external RF path IC can be connected to SAA7834 by selecting bit 1 of register

RFBypassSel. The input for the RF signal is then via pin HF_MON. In this mode the

central diode summing circuit, RF AMP1, high-pass ﬁlter and RF AMP2 are all bypassed.

6.2 Analog clock generation

The SAF784x consists of two analog phase-locked loops. The 67 MHz PLL is dedicated to

the channel decoder. The 152 MHz PLL is dedicated to the remaining functionality. The

clock strategy for the SAF784x is intended to address areas that are prone to noise effects

Fig 5.

Analog clock generation

001aag309

CLOCK MULTIPLIER

VARIABLE RATIO

OSC

CNTRL[4]

ADC

AUDIO

DAC

CLOCK MULTIPLIER

÷ 2

CNTRL[5]

CNTRL[1]

CNTRL[2]

CNTRL[3]

AnaClockPLLControl[3]

used for internal test

adac_in_8_clk

used for internal test

sys32k_clk

(real time clock)

micro_clk (152 MHz)

lfadc8m_clk

(digital servo)

pad_clk1v8

(used for

internal test)

AnaClockPLLControl[0]

ANALOG to DIGITAL

interface

PADS

pad_clk3v3

CNTRL[0]

OSC

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