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SAF784X 数据表(PDF) 75 Page - NXP Semiconductors

部件名 SAF784X
功能描述  One chip CD audio device with integrated MP3/WMA decoder
PDF  93 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

SAF784X 数据表(HTML) 75 Page - NXP Semiconductors

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SAF784X_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
75 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
7.11 Timers
• Conforms to the VLSI Peripheral Bus (VPB) interface specification
• Clock prescaler for external high-frequency sources
• The VPB timer operates in two fully independent clock domains:
– vpb_clk for accessing control and status registers (76 MHz maximum)
– timer_clk for the timer/counter function (50 MHz maximum)
• The VPB timer can support up to four match registers having:
– Continuous operation with optional interrupt generation on match
– Stop on match, with or without, interrupt generation
– Reset on match, with or without, interrupt generation
• Optional external match notification pins with the following features:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– No action on match
• Up to four capture registers and capture trigger pins with optional interrupt generation
on a capture event
• Interrupt generation on match event and capture event
7.12 Watchdog timer
• Configurable watchdog feature including:
– Watchdog timer restart trigger protection by key
– Watchdog timer reload value protection by key access sequence
– Watchdog timer reset disable (for debug) protection by key
• Interrupt generation watchdog time-out event
7.13 Real-time clock
• Zero wait-state to access all registers from the VPB interface
• Provide coherent fraction and seconds time
• Requirement for external 32 kHz crystal
• Alarm and tick interrupts will be generated even when the VPB clock is switched off
• VPB RTC interrupt
• Real-time clock and VPB clock may be asynchronous (the VPB clock frequency could
be higher or lower than the RTC clock frequency)
• Maximum VPB slave frequency: 50 MHz
7.14 DMA controller
The Single operation DMA interface (SDMA), is a small AHB bus master specifically
designed for bulk memory transfers over the ARM AHB bus.



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