SAF784X datasheet(70/93 Pages) NXP

70 / 93 page

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Fig 38. Default wait-state assertion during read from external memory

001aag349

address to

external

memory

13 ns cycle time (assuming

max frequency for cMusIC)

address from ARM

processor

read/write

control

address at

the memory

data read from

the memory

data read by

the arm

processor

output enable

/chip select

to the memory

access time of memory

normal 2 cycle delay, before data is read

by the ARM processor (when 0 wait states

programmed in SMBWST1Rx register;

1 wait state = 1 internal cycle)

data available

from the output of

memory

data from memory

read by ARM

processor

address seen on input of

external memory

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