SAF784X datasheet(27/93 Pages) NXP

27 / 93 page

SAF784X_2

Product data sheet

Rev. 02 — 9 May 2008

27 of 93

NXP Semiconductors

SAF784x

One chip CD audio device with integrated MP3/WMA decoder

The detection of a defect is based on amplitude. The amplitude is measured via a set of

peak detectors with decay, as described in Section “Peak Detectors” on page 23. The

decay bandwidth and noise ﬁlter bandwidth are programmed by register

DefectDetPeakBW.

Two thresholds can be programmed. A low threshold will trigger a ‘defect-detected’ signal

as soon as amplitude goes below this threshold. A high threshold will clear this

‘defect-detected’ signal again as soon as amplitude goes above this threshold. Together,

these thresholds apply a hysteresis to the defect detection, avoiding a jittery

‘defect-detected’ signal (having many on/off parts) when the amplitude is at the threshold

edge. Thresholds are programmed in register DefectDetThres.

The ‘defect-detected’ signal can be used to hold the PLL, slicer, AGC, AOC and HPF

during a defect. The feature(s) that will be held can be programmed in register

DefectDetEnables. The same register can be used, via software, to force the PLL, slicer

and HPF to hold. The AGC and AOC can be held in software by just disabling the loops in

Two special features exist on the defect detector:

• Optional delay of the enabling and disabling of hold features at the beginning and end

of a defect. This can be done by programming a start and/or stop delay (in number of

sysclks) via register DefectDetStartStopDelay. Whenever the defect detector detects

the start of a defect, it will wait for the start delay before triggering a ‘defect-detected

processed’ signal. When the defect detector detects the end of a defect, it will wait for

the programmed stop delay before clearing the defect-detected processed’ signal

again. This also means that defects which are smaller than the start delay are

ignored, and that if the defect contains zones with good RF amplitude but smaller than

the stop delay, they are also ignored. In reality, all hold features are triggered by the

defect-detected processed’ signal, rather than the ‘defect-detected’ signal; at the

decoder output, both delays are zero, so both signals are equal.

• Optional programmable time-window at the end of a defect, during which, higher PLL

and/or slicer bandwidths can be used to speed up the recovery of these loops after a

defect. This window can be programmed via register DefectDetHighBWDelay.

Bandwidth programming is explained in Section 6.5.5.2 on page 28.

The detection of the beginning or end of a defect, with or without start and stop delays,

can be used to generate an interrupt. See register InterruptEnable1.

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