SAF784X datasheet(31/93 Pages) NXP

31 / 93 page

SAF784X_2

Product data sheet

Rev. 02 — 9 May 2008

31 of 93

NXP Semiconductors

SAF784x

One chip CD audio device with integrated MP3/WMA decoder

• optional manual selection of the PLL state (in-lock, inner-lock, outer-lock, outer-lock

with only RL3 regulation).

• optional pre-set of the PLL frequency to a certain value

Overriding the PLL state: PLL state can be:

• In-lock

• Inner lock

• Outer lock

• Outer lock with only RL3 regulation

• Hold

Normally, the PLL state is selected automatically by the lock detectors. However, the PLL

lock state can be overruled via register PLLLockAidControl. When Lock mode is left at ‘0’,

the user can still choose the PLL state, but hardware will overwrite this if the

hardware-selected PLL state is closer to locking the PLL.

[1]

During PLL hold, the PLL frequency will not change and the frequency preset may be used.

It is possible to pre-set the PLL frequency to a certain value by writing the integrator value

of the PLL to register PLLIntegrator. The relationship between the bit frequency, the

integrator value, and the sysclk frequency fclk(sys) is given by:

(2)

The real-time value of the PLL frequency can be read at the same address.

6.5.5.3

Limiting the PLL frequency range

The range over which the PLL can capture the input frequency can be limited. The

minimum and maximum PLL frequency can be set by bits MININTFREQ, and

MAXINTFREQ respectively in register PLLMinMaxBounds.

6.5.5.4

Run length 2 push-back detector

If this circuit is switched on, all run length one and two symbols (invalid run lengths) are

pushed back to run length 3. For RL2s, the circuit will determine the transition that was

most likely to be in error, and shift transition on that edge. This feature should always be

turned on, but can be deselected via register RL2PushBack.

Table 5.

PLL lock states

Lock mode

PLLLockControl

State[1]

0 0000

automatic lock behavior

0 0001

force HF PLL into in-lock

0 0110

force HF PLL into inner-lock aid

0 0100

force HF PLL into outer-lock aid

0 1000

force HF PLL into hold mode

1 0100

force HF PLL into outer-lock aid with RL3 regulation only

others

reserved

clk bit

()ch

PLLFreq 7:0

[] 4

128

-----------------------------------------------

clk sys

()

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